Takashi Akioka

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Recent diversity in multicell upset (MCU) of CMOS SRAMs are reviewed and scaling effects are discussed. Space and time domain automatic classification techniques are developed and applied to single event upsets (SEUs) of 130nm SRAM under quasi-mono energetic neutron irradiation at TSL and CYRIC. Tests show very high dependency of MCU features on data(More)
In recent CMOS devices, multi-cell error induced by cosmic neutron, in which memory state change extends over multiple memory cells, is becoming serious. However, its mechanism has not been clarified yet because conventional analysis by device simulation has not included multiple memory cells domain. Our novel method is to create the device model including(More)
There are many memory technologies that are competing to become the mainstream nonvolatile memory solution. This session presents circuits and technology for some of these emerging memories, including ferroelectric RAM and phase change RAM. State-of-the-art design and testing techniques for 6T CMOS SRAM, novel architecture and circuit techniques for content(More)
This session presents trends in embedded and emerging memories including an overview of issues for advanced embedded SRAM and DRAM and discussion of high density FeRAM and tunnel junction MRAM. A novel gain cell using a single electron transistor for SRAM-type data storage is described along with a new ternary CAM macro and an on-chip programmable CMOS(More)
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