Takanori Okuma

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have enabled system-on-chip (SOC) designs in which a system’s entire functionality rests on a single chip. SOCs are embedded in various electric products, such as portable information terminals, digital audio systems, and automobiles. Many of these products are real-time systems with timing constraints. An important consideration in SOC design is minimizing(More)
This paper presents a real-time task scheduling technique with a variable voltage processor which can vary its supply voltage dynamically. Using such a processor, running tasks with a low supply voltage leads to drastic power reduction. However, reducing the supply voltage may violate real-time constraints. In this paper, we propose a scheduling technique(More)
In this paper, we propose instruction encoding techniques for embedded system design, which encode immediate fields of instructions to reduce the size of an instruction memory. Although our proposed techniques require an additional decoder for the encoded immediate values, experimental results demonstrate the effectiveness of our techniques to reduce the(More)
This paper presents a novel low-energy memory design technique, considering effective bitwidth of variables for application-specific systems, called VAbM technique. It targets the exploitation of both data locality and effective bitwidth of variables to reduce energy consumed by redundant bits. Under constraints of the number of memory banks, the VAbM(More)
We describe our 3-D museum guide system and the pilot study we did to evaluate it. The prototype system used in the pilot study uses a human positioning system based on dead reckoning, active RFIDs, and map matching. The system manages content consisting of 3-D maps, recommended routes, and Flash files to provide appropriate navigation information based on(More)
This paper presents a new concept called active data bitwidth, which is the effective data length of data bus. By means of profiling the active data bitwidth dynamically, we present a novel low-energy memory access technique for on-chip data memory design. By reducing the redundant access energy of data memory, our experimental results of two real(More)
A case study of human-behavior sensing in a Japanese cuisine restaurant is described. The aim of this study is to create a suite of human-behavior sensing that facilitate people who are in real service fields to understand current operations, and make plans for improving operations. We created a prototype of the suite, which consists of several component(More)
We are proposing "PPRAM-Link": a new high-speed communication standard for merged-DRAM/logic SoC architecture. PPRAM-Link standard is composed of physical/logical layers and an API for the upper software layer, which are standardized by PPRAM Consortium. We developed a PPRAM-Link Interface IP family, or "PLIF Core" that realizes logical protocols necessary(More)
To transfer a small number, we inherently need the small number of bits. But all bit lines on a data bus change their status and redundant power is consumed. To reduce the redundant power consumption, we introduce a concept named active bits. In this paper, we propose a power reduction scheme for data buses using the active bits. Suppressing switching(More)
This paper presents a real-time OS based on μITRON using proposed voltage scheduling algorithm for variable voltage processors which can vary supply voltage dynamically. The proposed voltage scheduling algorithms assign voltage level for each task dynamically in order to minimize energy consumption under timing constraints. Using the presented real-time OS,(More)