Takanori Hayashida

  • Citations Per Year
Learn More
MultiCore Processor System-on-Chip (MPSoC) is one of the promising technique to satisfy computing demands of the future consumer devices. While MPSoC has an advantage in energy consumption in comparison with high-frequency microprocessor-based system, it is still threatened by increasing energy consumption due to process-voltage-temperature (PVT)(More)
MultiCore processor is one of the promising techniques to satisfy computing demands of the future consumer devices. However, MultiCore processor is still threatened by increasing energy consumption due to PVT (Process-Voltage-Temperature) variations. They require large design margins in the supply voltage, resulting in large energy consumption. The(More)
* The preliminary results of this study were presented as a fast abstract at PRDC 2010 [1]. Abstract The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial(More)
Multicore processor is one of the promising techniques to satisfy computing demands of the future consumer devices. Dynamic voltage scaling (DVS) technique is a mature power reduction technique. Unfortunately, when they are combined, the efficiency in power reduction is mitigated as the number of cores on a chip increases. Furthermore, multicore processor(More)
This paper first investigates what the best multicore configuration will be in the future, when the number of usable transistors further increases. Comparing five multicore models: single-core, many-core, heterogeneous multicore, scalable homogeneous multicore, and dynamically configurable multicore, surprisingly unveils that single-core performance is a(More)
Soft error rate (SER) of various radiation hardened latches is analyzed by simulation. SER is estimated by modeling the variety of current pulses triggered by particle strikes such as neutrons from space or alpha particles using Monte Carlo method. By using proposed method, we show that SER of various latches is accurately analyzed without conducting(More)
This paper investigates a possible architecture to a dynamically adaptable processor. In this architecture, the running application is profiled and dynamic traces of high frequently executed loops (hot paths) are detected. The proposed online profiling methodology is mainly hardware-based so that overhead can be reduced as much as possible. Studying the(More)
Negative Bias Temperature Instability (NBTI) is one of the dominant factors determining a device lifetime. NBTI causes a threshold voltage shift on a PMOS transistor. Modern LSI often has large on-chip SRAMs such as cache memories. NBTI affects the SRAM cell as degradation in Static Noise Margin (SNM), which is a measure of the read stability of the cell.(More)
  • 1