Takafumi Fukushima

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— This Paper presents on 3D stacking technology with 2.5μm x 2.5μm In (Indium) bump connections with adhesive injection [1]. Instead of using the simple test device, this technology has been verified using the actual circuit level test chip. And it was found that the completion of stacking process is affected by the layout pattern of stacked each tier. In(More)
A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have(More)
Prior research suggests that predicting defect-inducing changes, i.e., Just-In-Time (JIT) defect prediction is a more practical alternative to traditional defect prediction techniques, providing immediate feedback while design decisions are still fresh in the minds of developers. Unfortunately, similar to traditional defect prediction models, JIT models(More)
Unlike traditional defect prediction models that identify defect-prone modules, Just-In-Time (JIT) defect prediction models identify defect-inducing changes. As such, JIT defect models can provide earlier feedback for developers, while design decisions are still fresh in their minds. Unfortunately, similar to traditional defect models, JIT models require a(More)
New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D) and hetero integration of complementary metal-oxide semiconductors (CMOS) and microelectromechanical systems (MEMS). By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF) aqueous(More)
Chip-to-wafer bonding is a promising technology for 3D integration due to high production yield using known good dies (KGDs). However, conventional chip-to-wafer 3D integration lowers production throughput because pick-and-place chip assembly is employed. To overcome the problem, we proposed a new chip-to-wafer 3D integration using self-assembly by which(More)