Takaaki Tatsumi

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For the purpose of 90nm technology node RF CMOS geometry optimization, the effect of geometrical variations on the high frequency characteristics are precisely analyzed utilizing a three dimensional TCAD device simulator. After showing the accuracy of small-signal 3D TCAD simulation, the dependence of MOSFET's gate resistance on gate width is analyzed with(More)
High frequency noise issues with scaled MOSFETs are calculated and analyzed for the purpose of structure optimization utilizing a three dimensional TCAD device simulator, and the following results have been revealed: for the transistors with a gate length less than 100 nm, the induced gate noise becomes very sensitive to the gate width because of the higher(More)
We have developed a JAVA based novel system called NILE, which is tolerable for practical use and working on a distributed environment for semiconductor process and device simulations. NILE enables the utilization of simulation in practical use from remote sites even if the network bandwidth is narrow. NILE has succeeded to provide a same kind of simulation(More)
Our new ESD design methodology use gate work function control and channel length optimization. We developed a P/N hybrid gate NMOS, where P gate in the channel region reduces subthreshold leakage current thanks to a higher Vth, and N gate in the overlap region reduces GIDL thanks to a lower electric field.
We have developed a novel and effective method for predicting the distribution of MOSFET device characteristics, which also enables us to specify the most typical process conditions for any device characteristics. In our approach, the distribution of the device characteristic caused by the fluctuation of every single process are calculated and then merged.(More)
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