Taimur Gibran Rabuske

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Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this paper, we(More)
Analog designers are challenged by increasingly complex device models and lowered signal swing as the CMOS processes scale. At the same time, new trends and emerging technologies pose tighter design constraints. However, the cheap computational resources nowadays enable the use of the mature electrical simulators and device models in simulation-in-a-loop(More)