Tai-Hung Liu

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Pass Transistor Logic (PTL) circuits have been successfully used to implement digital ICs which are smaller, faster, and more energy efficient that static CMOS implementations of the same designs. Thus far, most PTL implementations have been handcrafted; as such, designer acceptance of PTL has been limited. In this paper, we develop efficient algorithms for(More)
For many digital designs, implementation in passtransistor logic (PTL) has been shown to be superior in terms of area, timing, and power characteristics to static CMOS. Binary Decision Diagrams (BDDs) have been used for PTL synthesis because of the close relationship between BDDs and PTL. Thus far, BDD optimization for PTL synthesis has targeted minimizing(More)
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