—A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers. Designed in a 0.4-m CMOS technology, the circuit employs an LMS algorithm to adapt… (More)
A stabilization technique is presented that relaxes the trade-off between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay cell, obviating the need for resistors in the loop filter.
—A dual-operation-mode ring oscillator that employs dual-delay paths is presented. The two operation modes, referred to as the differential and common modes, have different output waveform characteristics and oscillation frequencies. A nonlinear model for the dual-delay-path ring oscillator and the analysis of the stability of each operation mode are… (More)
—A discrete-time mixed-signal Gaussian frequency shift keying demodulator designed for a low intermediate frequency Bluetooth receiver performs FSK demodulation. Employing passive sampling and time-domain differentiation techniques, the demodulator performs quadrature demodulation while tolerating up to 200-kHz frequency offset. A distributed array of… (More)
• The concept of the two-stage and folding ADC: