Tai-Cheng Lee

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A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers. Designed in a 0.4m CMOS technology, the circuit employs an LMS algorithm to adapt to(More)
A discrete-time mixed-signal Gaussian frequency-shift keying demodulator designed for a low intermediate frequency Bluetooth receiver performs FSK demodulation. Employing passive sampling and time-domain differentiation techniques, the demodulator performs quadrature demodulation while tolerating up to 200-kHz frequency offset. A distributed array of(More)
A dual-operation-mode ring oscillator that employs dual-delay paths is presented. The two operation modes, referred to as the differential and common modes, have different output waveform characteristics and oscillation frequencies. A nonlinear model for the dual-delay-path ring oscillator and the analysis of the stability of each operation mode are(More)
A 6-b 1.3-Gs/s pipelined successive-approximation analog-to-digital converter (ADC) is presented. Employing improved-MMS and C-2C architecture, the circuit operates in high speed and low power consumption. With open-loop architecture, the T/H circuit can work at a high conversion rate. The proposed architecture reduces the static power consumption by charge(More)
An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. The clock skew problem is detrimental in high-speed applications, especially when the skew is longer than multi-cycles. The proposed clock generator was fabricated in a 0.18-μm CMOS(More)