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This paper presents several optimization algorithms for a High Efficiency Video Coding (HEVC) encoder based on single instruction multiple data (SIMD) operations and data-level parallelism. Based on the analysis of the computational complexity of HEVC encoder, we found that interpolation filter, cost function, and transform take around 68% of the total(More)
Load balancing algorithm supporting parallel tools for HEVC encoder is proposed in this paper. Standardization of HEVC version 1 was finalized and which is known that its RD performance is two times better than H.264/AVC which was the most efficient video coder. However, computational complexity of HEVC encoding process derived from variable block sizes(More)
The power consumption of a digital circuit can be reduced by decomposing it into sub circuits which can be turned off when inactive. Power can also be reduced by careful state encoding. Clock-gating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits. Modeling a given circuit as a(More)
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