Tae-Gyoung Kang

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A 1.2 V 72 Mb DDR3 SRAM in a 0.10 /spl mu/m CMOS process achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines reduce the power dissipation and the number of data lines by half. Clocks phase-shifted by 0/spl deg/, 90/spl deg/ and 270/spl deg/ are generated by clock adjustment circuits. On-chip input termination(More)
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