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Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins
To solve the problem of fluctuations in clock timing with digital LSI (also known as the "clock skew" problem), we propose a genetic algorithm (GA) based clock adjustment method that ensures robustExpand
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Measurements of $$\pi ^\pm $$π± differential yields from the surface of the T2K replica target for incoming 31 GeV/c protons with the NA61/SHINE spectrometer at the CERN SPS
Measurements of particle emission from a replica of the T2K 90 cm-long carbon target were performed in the NA61/SHINE experiment at CERN SPS, using data collected during a high-statistics run inExpand
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Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins
To solve the problem of fluctuations in clock timing with digital LSIs (also known as the "clock skew" problem), we propose a genetic algorithm (GA) based clock adjustment method that ensures robustExpand
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Electromagnetic behavior on high-temperature superconducting bulk YBCO exposed to time-varying magnetic field
The authors present the results of a comprehensive study of the electromagnetic behavior of high-temperature superconducting bulk YBCO exposed to a time-varying magnetic field. The characteristic ofExpand
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Transient stability of AC multi-strand superconducting cables
Abstract AC application, it is necessary to estimate the stability of multi-strand superconducting cable. Therefore, we have been studying the transient stability of non-insulated multi-strand cableExpand
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A low-power DCT chip utilizing post-fabrication clock-timing adjustment with area reductions and adjustment speed enhancements
A new post-fabrication clock-timing adjustment method using a genetic algorithm (GA) has been proposed to improve the performance of sub-100 nm LSIs. In the new method, we propose a new technique forExpand
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An Additional 12% Power Reduction in Practical Digital Chips with a Low-Power Design Using Post-Fabrication Clock-Timing Adjustment
In order to solve the clock-skew problem, which becomes more and more serious for sub-100 nm processes, we have proposed a post-fabrication clock-timing adjustment technique and have been improvingExpand