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On-chip memory architecture exploration framework for DSP processor-based embedded system on chip
TLDR
We address the memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. Expand
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Optimal code and data layout in embedded systems
TLDR
Efficient layout of code and data sections in various types/levels of memory in an embedded system is very critical not only for achieving real-time performance, but also for reducing its cost and power consumption. Expand
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Memory Architecture Exploration Framework for Cache Based Embedded SOC
TLDR
We address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. Expand
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MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
TLDR
We present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Expand
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On-Chip Memory Architecture Exploration of Embedded System on Chip
TLDR
In this work, we propose an automated framework for on-chip memory architecture exploration and data layout to search the design space efficiently. Expand
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MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
TLDR
We address the multi-level multi-objective memory architecture exploration problem through a combination of Multi- objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. Expand
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