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NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
  • L. Chen, T. Pinkston
  • Computer Science
  • 45th Annual IEEE/ACM International Symposium on…
  • 1 December 2012
While power-gating is a promising technique to mitigate the increasing static power of a chip, a fundamental requirement is for the idle periods to be sufficiently long to compensate for theExpand
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Power punch: Towards non-blocking power-gating of NoC routers
As chip designs penetrate further into the dark silicon era, innovative techniques are much needed to power off idle or under-utilized system components while having minimal impact on performance.Expand
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A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime
Microarchitectural redundancy has been proposed as a means of improving chip lifetime reliability. It is typically used in a reactive way, allowing chips to maintain operability in the presence ofExpand
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DISHA: a deadlock recovery scheme for fully adaptive routing
This paper presents a simple method of implementing an efficient and cost effective routing scheme. The strategy considers deadlock recovery as opposed to prevention to optimize performance in theExpand
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An efficient, fully adaptive deadlock recovery scheme: DISHA
This paper presents a simple, efficient and cost effective routing strategy that considers deadlock recovery as opposed to prevention. Performance is optimized in the absence of deadlocks by allowingExpand
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Critical Bubble Scheme: An Efficient Implementation of Globally Aware Network Flow Control
Network flow control mechanisms that are aware of global conditions potentially can achieve higher performance than flow control mechanisms that are only locally aware. Owing to high implementationExpand
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A General Theory for Deadlock-Free Adaptive Routing Using a Mixed Set of Resources
This paper presents a theoretical framework for the design of deadlock-free fully adaptive routing algorithms for a general class of network topologies and switching techniques in a single, unifiedExpand
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Software-based deadlock recovery technique for true fully adaptive routing in wormhole networks
In this paper, we take a different approach to handle deadlocks and performance degradation. We propose the use of an injection limitation mechanism that prevents performance degradation near theExpand
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A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
Survival capability is becoming a crucial factor in designing multicore processors built with on-chip packet networks, or networks on chip (NoCs). In this paper, we propose a lightweightExpand
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Deadlock-Free Dynamic Reconfiguration Schemes for Increased Network Dependability
Network-based parallel computing systems often require the ability to reconfigure the routing algorithm to reflect changes in network topology if and when voluntary or involuntary changes occur. TheExpand
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