T. Anand

A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. Expand

A self-referenced VCO-based temperature sensor with reduced supply sensitivity is presented. Expand

A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital frequency-tracking loop (FTL) with theoretical large-signal analysis for phase domain response (PDR). Expand

This paper demonstrates an on-chip electrical cold-start technique to achieve low-voltage and fast start-up of a boost converter for autonomous thermal energy harvesting from human body heat. Expand

We present an automatic frequency acquisition scheme that has unlimited range and is immune to variations in transition density. Expand

In this paper, the authors present a digital frequency tracking loop (FTL) to continuously tune the oscillator free running frequency FFR to be NFREF. Expand

A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. Expand

A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. Expand

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. Expand