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- Publications
- Influence
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
- A. Elkholy, T. Anand, Woo-Seok Choi, A. Elshazly, P. Hanumolu
- Physics, Computer Science
- IEEE Journal of Solid-State Circuits
- 29 January 2015
TLDR
A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity
- T. Anand, K. Makinwa, P. Hanumolu
- Materials Science, Computer Science
- IEEE Journal of Solid-State Circuits
- 8 September 2016
TLDR
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers
- A. Elkholy, M. Talegaonkar, T. Anand, P. Hanumolu
- Engineering, Computer Science
- IEEE Journal of Solid-State Circuits
- 13 October 2015
TLDR
Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-Voltage Ring Oscillator
- S. Bose, T. Anand, M. Johnston
- Physics, Medicine
- IEEE Journal of Solid-State Circuits
- 8 August 2019
TLDR
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS
- G. Shu, Woo-Seok Choi, Saurabh Saxena, T. Anand, A. Elshazly, P. Hanumolu
- Computer Science
- IEEE International Solid-State Circuits…
- 6 March 2014
TLDR
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS
- A. Elkholy, M. Talegaonkar, T. Anand, P. Hanumolu
- Physics, Computer Science
- IEEE International Solid-State Circuits…
- 19 March 2015
TLDR
Integrated-Jitter PVT-Insensitive Injection-Locked Clock Multiplier Using All-Digital Continuous Frequency-Tracking Loop in 65 nm CMOS
Sub-harmonically injection locked oscillators provide a simple means for generating very-low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free-running… Expand
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- PDF
An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording
- Vikram Chaturvedi, T. Anand, B. Amrutur
- Computer Science
- IEEE Transactions on Very Large Scale Integration…
- 1 November 2013
TLDR
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition
- G. Shu, Woo-Seok Choi, +5 authors P. Hanumolu
- Computer Science
- IEEE Journal of Solid-State Circuits
- 1 February 2016
TLDR
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method
- R. Nandwana, T. Anand, +6 authors P. Hanumolu
- Physics, Computer Science
- IEEE Journal of Solid-State Circuits
- 3 February 2015
TLDR