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A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity

A self-referenced VCO-based temperature sensor with reduced supply sensitivity and a novel sensing technique in which temperature information is acquired by evaluating the ratio of the output frequencies of two ring oscillators, designed to have different temperature sensitivities, thus avoiding the need for an external frequency reference.
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A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution and is less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL.
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Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-Voltage Ring Oscillator

An on-chip electrical cold-start technique to achieve low-voltage and fast start-up of a boost converter for autonomous thermal energy harvesting from human body heat is demonstrated.
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Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

This paper introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection-locked oscillators (ILOs) and captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance.
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A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth…
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A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs.
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8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS

An automatic frequency-acquisition scheme that has unlimited range and is immune to variations in transition density is presented, using a ring-oscillator-based fractional-N PLL as a digitally controlled oscillator (DCO) to achieve both wide range and low noise.
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10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS

A digital frequency-tracking loop (FTL) to continuously tune the oscillator free running frequency FFR to be NFREF to ensure robust operation of the ILCM across PVT variations even with a very narrow lock-in range and enables its implementation using large N and high-Q LC DCO.
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A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links

A rapid-on/off transceiver for embedded clock architecture that enables energy proportional communication over the serial link that demonstrates power scalability with a wide range of link utilization and, therefore, helps in improving overall system efficiency.
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Fully-integrated 57 mV cold start of a thermoelectric energy harvester using a cross-coupled complementary charge pump

This work demonstrates cold-start of a thermoelectric energy harvester at the lowest input voltage reported to date for a fully-integrated solution.
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