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A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
TLDR
A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. Expand
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A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity
TLDR
A self-referenced VCO-based temperature sensor with reduced supply sensitivity is presented. Expand
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Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers
TLDR
A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital frequency-tracking loop (FTL) with theoretical large-signal analysis for phase domain response (PDR). Expand
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Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-Voltage Ring Oscillator
TLDR
This paper demonstrates an on-chip electrical cold-start technique to achieve low-voltage and fast start-up of a boost converter for autonomous thermal energy harvesting from human body heat. Expand
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8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS
TLDR
We present an automatic frequency acquisition scheme that has unlimited range and is immune to variations in transition density. Expand
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10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS
TLDR
In this paper, the authors present a digital frequency tracking loop (FTL) to continuously tune the oscillator free running frequency FFR to be NFREF. Expand
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Integrated-Jitter PVT-Insensitive Injection-Locked Clock Multiplier Using All-Digital Continuous Frequency-Tracking Loop in 65 nm CMOS
Sub-harmonically injection locked oscillators provide a simple means for generating very-low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free-runningExpand
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An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording
TLDR
A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. Expand
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A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition
TLDR
A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. Expand
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A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method
TLDR
A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. Expand
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