T. Srikanthan

Learn More
Reconfigurable processors provide an attractive means to meet the constraints of embedded devices due to their instruction set extension capabilities. We propose a novel technique to estimate the area utilization of LUT (Look-Up Table) based FPGAs (Field Programmable Gate Arrays) for custom instruction realizations. The technique contributes to rapid design(More)
As embedded systems evolve, there is greater dependency on the real-time operating system (RTOS) to abstract the complex hardware. In return for the services provided, the RTOS consumes CPU cycles, thereby imposing a processing overhead on the CPU. In this paper, we review some of the techniques that have been proposed in literature for reducing the CPU(More)
The presence of different types of noise during enrollment and verification phase results in severe performance degradation in speaker verification systems. Spectral subtraction is a speech enhancement method which is often used to estimate the clean speech. However, spectral subtraction loses its accuracy in the frames with low signal-to-noise-ratio. In(More)
In recent years, embedded systems have become increasingly more complex. This complexity is tackled in software by abstracting the underlying hardware using an embedded real-time operating system (RTOS) and a suitable board support package (BSP). However, the RTOS imposes overheads on the CPU in return for the run-time support it provides. Modern embedded(More)
It has only been very recently that commercial asynchronous processors on FPGAs have started to take shape, and much of the design details of the architecture prototypes are not publicly available. Programming description languages and CAD tools for asynchronous design are still maturing, and there are different languages like CSP, Tangram, OCCAM, Verilog+,(More)
This paper reports how VLSI cost metrics (area, delay, power) of residue reverse converters scale with the cardinality and dynamic range of moduli sets. The study uses CMAC reverse converters, reported previously by the authors to be the most efficient known to date in terms of area and delay. In all, 134 reverse converters with dynamic ranges from 32 to(More)
Filter cache (FC) is an auxiliary cache much smaller than the main cache. The FC is closest in hierarchy to the instruction fetch unit and it must be small in size to achieve energy-efficient realisations. A pattern prediction scheme is adapted to maximise energy savings in the FC hierarchy. The pattern prediction mechanism proposed relies on the spatial(More)