T. Srikanthan

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Reconfigurable processors provide an attractive means to meet the constraints of embedded devices due to their instruction set extension capabilities. We propose a novel technique to estimate the area utilization of LUT (Look-Up Table) based FPGAs (Field Programmable Gate Arrays) for custom instruction realizations. The technique contributes to rapid design(More)
The presence of different types of noise during enrollment and verification phase results in severe performance degradation in speaker verification systems. Spectral subtraction is a speech enhancement method which is often used to estimate the clean speech. However, spectral subtraction loses its accuracy in the frames with low signal-to-noise-ratio. In(More)
It has only been very recently that commercial asynchronous processors on FPGAs have started to take shape, and much of the design details of the architecture prototypes are not publicly available. Programming description languages and CAD tools for asynchronous design are still maturing, and there are different languages like CSP, Tangram, OCCAM, Verilog+,(More)
Filter cache (FC) is an auxiliary cache much smaller than the main cache. The FC is closest in hierarchy to the instruction fetch unit and it must be small in size to achieve energy-efficient realisations. A pattern prediction scheme is adapted to maximise energy savings in the FC hierarchy. The pattern prediction mechanism proposed relies on the spatial(More)
Residue number system is popular in high performance arithmetic applications like digital signal processing because of its carry free nature, modularity and error correcting properties. But these opportunities are eclipsed by the high area and time requirements for reverse conversion. In this regard, we present two new techniques for residue-to-weighted(More)
Most asynchronous processor ISA (instruction set architecture) implementations are based on only one type of asynchronous design style. The ISA is dependent on the type of asynchronous design style chosen and is optimized to support a particular set of applications. Design reuse is typically difficult to realize in these cases. In this paper, we share some(More)