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A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only(More)
Variability is an important aspect of SRAM cell design. Failure probabilities of P<sub>fail</sub>les10<sup>-10</sup> have to be estimated through statistical simulations. Accurate statistical techniques such as Importance Sampling Monte Carlo simulations are essential to accurately and efficiently estimate such low failure probabilities. This paper shows(More)
Photovoltaic (PV) systems are increasingly used to generate electrical energy from solar irradiance incident on PV modules. Each PV module is formed by placing a large amount of PV cells, typically 60, in series. The PV system is then formed by placing a number, typically 10-12, of PV modules in series in a string and sometimes by placing multiple strings(More)
New insights in the programming physics of silicided polysilicon fuses integrated in 90 nm CMOS have led to a programming time of 100 ns, while achieving a resistance increase of 10<sup>7</sup>. This is an order of magnitude better than any previously published result for the programming time and resistance increase individually. Simple calculations and(More)
This work presents a power management IC used to mitigate the effects of mismatch in Concentrating-Photovoltaic (CPV) systems. The IC contains a bi-directional dc-dc converter, an auxiliary boost converter to generate the internal 10 V power supply, as well as protection and monitoring circuits. The main power converter, with a maximum current rating of 1.5(More)
V<sub>t</sub>-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to radically different SRAM characteristics. By(More)
This paper presents a detailed qualitative model for the programming physics of 90-nm silicided polysilicon fuses that is derived from a wide range of measurement data. These insights have led to a programming time of 100 ns, while achieving a resistance increase of times. This is an order of magnitude better than any previously published result for the(More)
Photovoltaic (PV) installations suffer from a disproportional decrease in output power in case irradiance differences are present in the system. The Delta converter improves the output power in such cases by routing current differences around the shaded substring or module. This paper presents a driver IC for the Delta converter that simultaneously reduces(More)
A product may fail when design parameters are subject to large deviations. To guarantee yield one likes to determine bounds on the parameter range such that the fail probability P<sub>fail</sub> is small. For Static Random Access Memory (SRAM) characteristics like Static Noise Margin and Read Current, obtained from simulation output, are important in the(More)
For robust design of SRAM memories, it is not sufficient to guarantee good statistical margins on the SRAM cell parameters. The sense amplifier needs sufficient input signal before it can reliably sense the data, while the SRAM cell requires sufficient time to develop that input signal. This paper presents a new statistical method that allows optimization(More)
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