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—This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage V T platform for digital circuits compatible with bulk complementary metal–oxide–semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were(More)
For the first time, we report fully depleted SOI MOS transistors with WSi<sub>x</sub> gate on HfO<sub>2</sub>. Gate work function, dielectric properties and channel mobility are presented in terms of Si/W ratio and compared to TiN gate devices. A 35% electron mobility gain was obtained with a WSi<sub>x</sub> gate device as compared to a TiN gate transistor.(More)
We demonstrate that Fully Depleted Silicon-On-Insulator (FDSOI) technology is a simple and mature alternative to the bulk one for the 22nm technology node and beyond. In particular, this technology allows significant improvement of the transistors electrostatic control and variability. Furthermore, the integration of such FDSOI transistors on an ultra-thin(More)
Since the end of the last millenium, the microelectronics industry is facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS devices structure or if new devices architectures are implemented. The demand for low voltage, low power and high performance are the great(More)
We present a model of quantum transport for Si nanowire transistor that makes use of the Wigner function formalism and takes into account carrier scattering. Scattering effects on current-voltage (I&#x2013;V) characteristics are assessed using both the relaxation time approximation and the Boltzmann collision operator. Within the Fermi golden rule(More)
We report in this paper the fabrirication and the characterirization of FDSOI pMOSFETs with metallic source and drain exhibiting the best performance obtained so far on metallic source/drain devices, with Ion=345&#x00B5;A/&#x00B5;m and Ioff=30nA/&#x00B5;m at &#x2212;1V for a 50nm gate length device. These results have been achieved thanks to a careful(More)
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