T. K. Bhattacharyya

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— The paper reports the implementation of a frequency synthesizer for system-on-chip (SOC) design. The epi-digital CMOS process is used to provide SOC solution. This work focuses on low-power consumption to achieve longer lifetime of batteries. A 2.4GHz frequency synthesizer has been fabricated in 0.18µm epi-digital CMOS technology for ZigBee applications,(More)
In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by(More)
Over the past few years, microelectromechanical system (MEMS) based on-chip resonators have shown significant potential for sensing and high frequency signal processing applications. This is due to their excellent features like small size, large frequency-quality factor product, low power consumption, low cost batch fabrication, and integrability with CMOS(More)
This article presents the design of a novel quadband LNA operating in the GSM 0.9GHz/GSM l.8GHz and ZigBee 0.9GHz/WLAN 2.4GHz communication standards. This pseudo-concurrent architecture uses a two bit mode switch for selecting between the frequency bands. An RF switch is implemented before the Low Noise Amplifier (LNA) module to improve the insertion loss(More)
A fully-integrated, ZigBee standard compliant, frequency synthesizer in the frequency range of 2.4-2.4835 GHz with frequency resolution of 5MHz, is designed in 0.18mum epi-CMOS process and silicon performance is measured. Integer-N architecture is chosen for implementation. It consumes 7.95mW of power at 1.8V supply and core area is(More)