T. Duong

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ABSTRACf Cascadable, CMOS synapse chips containing a crossbar array of 32x32 (1024) programmable synapses have been fabricated as "building blocks" for fully parallel implementation of neural networks. The synapses are based on a hybrid digital-analog design which utilizes on-Chip 7-bit data latches to store quantized weights and two-quadrant multiplying(More)
BACKGROUND The National Hospital of Pediatrics in Vietnam performed >200 exchange transfusions annually (2006-08), often on infants presenting encephalopathic from lower-level hospitals. As factors delaying care-seeking are not known, we sought to study care practices and traditional beliefs relating to neonatal jaundice in northern Vietnam. METHODS We(More)
This paper introduces multihop relay system where the benefits of spatial diversity are achieved from the concurrent reception of signals that have been transmitted by multiple terminals. Amplify and forward cooperative relays will be used in this system. It will be obvious that multihop system can effectively mitigate the performance deterioration caused(More)
This paper presents an overview of current ongoing research and design efforts conducted by Intelligent Optical Systems, Inc. in the area of hardware-based color segmentation. We discuss the specifics of the design of a microchip that combines a hardwired hybrid neural network with on-chip color imaging. Several preliminary tests show high approximation(More)
Paper maps are an important but unwieldy data format. To increase its utility, copious amounts of map data have been scanned into a digital map knowledge base. The next task in this knowledge base is to reduce this data to its underlying feature form suitable for analysis. The size of the task requires high speed, at least at the 60,000 pixels per second(More)
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