T. Duong

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Hardware to implement feedforward neural networks has been developed for the evaluation of learning algorithms and prototyping of applications. To allow the construction of networks with arbitrary architectures, CMOS VLSI building-block components (e.g. arrays of neurons and synapses) have been designed. These can be cascaded to form networks with hundreds(More)
ABSTRACf Cascadable, CMOS synapse chips containing a crossbar array of 32x32 (1024) programmable synapses have been fabricated as "building blocks" for fully parallel implementation of neural networks. The synapses are based on a hybrid digital-analog design which utilizes on-Chip 7-bit data latches to store quantized weights and two-quadrant multiplying(More)
An electronic neural network for the Euclidean distance minimization problem, implemented in VLSI-based hardware, is described. The convergence properties of the neural-network hardware are investigated and compared with computer simulation results. The neural network's ability to find the 'best' or a 'good' solution is quickly demonstrated. The effect of(More)
Paper maps are an important but unwieldy data format. To increase its utility, copious amounts of map data have been scanned into a digital map knowledge base. The next task in this knowledge base is to reduce this data to its underlying feature form suitable for analysis. The size of the task requires high speed, at least at the 60,000 pixels per second(More)
This paper presents an overview of current ongoing research and design efforts conducted by Intelligent Optical Systems, Inc. in the area of hardware-based color segmentation. We discuss the specifics of the design of a microchip that combines a hardwired hybrid neural network with on-chip color imaging. Several preliminary tests show high approximation(More)
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