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In this work, we demonstrate a 6.9 sq. /spl mu/m embedded SRAM cell in a 0.25 /spl mu/m physical design-rule salicide high-performance CMOS technology. The scalability of this salicide-CMOS embedded-SRAM technology is demonstrated by functionality of the same SRAM cell implemented in 0.35 /spl mu/m and 0.25 /spl mu/m design rules. To our knowledge this is(More)
An overview is given of plasma-etch processes used in microelectronics fabrication for pattern transfer, and the main requirements for plasma-assisted etching are outlined. The two primary etch mechanisms-chemical and physical-are examined. Issues involved in bringing plasma processes to the factory are discussed. Monitoring and controlling plasma processes(More)
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