Szu-Tsung Cheng

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We explore two ways of incorporating parallelism into priority queues. The rst is to speed up the execution of individual priority operations so that they can be performed one operation per time step, unlike sequential implementations which require O(log N) time steps per operation for an N element heap. We give an optimal parallel implementation that uses(More)
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now gaining acceptance in advanced design groups. This has been facilitated by the use of binary decision diagrams (BDDs). This paper describes the essential features of HSIS, a(More)
The lack of formal semantics for HDLs has made it hard to make a formal bridge between simulation tools based on HDLs and synthe-sis/verification tools based on finite state machines. In this paper we address the problem of finding a larger subset of Verilog HDL (which includes timing constructs) and a systematic way of extracting FSMs from programs built(More)
Category: B Intended for publication in the formal proceedings. All appropriate clearances for the publication of this paper have been obtained, and if accepted the author will prepare the final manuscript in time for inclusion in the Conference Proceedings and will present the paper at the conference. Summary VIS (Verification Interacting with Synthesis)(More)
We address the problem of formally proving properties of digital sequential systems. Speciically, our research is fo-cused on building an integrated framework, called HSIS, for supporting automatic approaches to formal design ver-iication. Our long term goal is to produce an industrial-strength tool that can be applied to complex systems. Such a tool would(More)
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