Sylvain Brunetton

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This paper presents a multimedia processor based on a SIMD architecture optimized for block based video processing algorithms. The processor, called DGP (Digital Generic Processor), is a generic system architecture, constituted by an array of pixel processors (SIMD) and a RISC controller. It is able to execute various video processing algorithms such as(More)
The implementation of software based video decoders is an advantageous solution over traditional dedicated hardware real time systems. The main reason of this fact is the possibility of decoding several different video compression standards, at different levels and profiles, by just changing the software while using the same hardware platform, main memory,(More)
This paper presents a new technique capable of predicting the processing time of video decoding tasks. Such technique is based on the collection and transmission in the compressed video bit-stream, of a suitable statistic information relative to the decoding process. Simulation results show that very accurate decoding time predictions can be obtained(More)
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