Sying-Jyan Wang

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Call packing has been recognized as a routing scheme that<lb>significantly reduces the blocking probability of connection requests in<lb>a circuit-switched Clos multistage interconnection network. In this brief<lb>contribution, for the first time, we develop general analytical models for<lb>the point-to-point blocking probability of the call-packing scheme(More)
Self-checking circuits can detect the presence of both transient and permanent faults. A self-checking circuit consists of a functional circuit, which produces encoded output vectors, and a checker, which checks the output vectors. The checker has the ability to expose its own faults as well. The functional circuit can be either combinational or sequential.(More)
We propose a structured design methodology to construct FSM-based programmable memory BIST. The proposed BIST can be programmed on-line, with a “macro command”, to select a test algorithm from a predetermined set of algorithms that are built in the memory BIST. In general, there are a variety of heterogeneous memory modules in SOC, and it is not possible to(More)
Since Field programmable gate arrays (FPGAs) are reprogrammable, faults in them can be easily toleruted once fault sites are located. Previous researches on diagnosis of FPGAs mainly deal with faulty logic block. In this paper we present a method for the testing and diagnosis of faults in the interconnect structures of FPGAs. A predefined set of tests that(More)
Power management has become a great concern in VLSI design in recent years. In this paper, we consider the logic level design technique for low power applications. We present a retiming-based optimization method, in which part of the circuit is selected and moved so that it produces logic signals one clock cycle before they are actually applied. If these(More)
A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low(More)
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Launch-off-shift (LOS) is a popular delay test technique for scan-based designs. However, it is usually not possible to achieve good delay fault coverage in LOS test due to conflicts in test vectors. In this article, we propose a layout-based scan chain ordering method to improve fault coverage for LOS test with limited routing overhead. A fast and(More)