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—An efficient architecture for a multi-resolution symmetrically extended 2-D 9/7 filter discrete wavelet transform processor is presented in this paper. Hardware complexity is greatly reduced with improved performance, thanks to the proposed combination of lifting scheme and line based architecture. Synthesizing the proposed design on a Xilinx Virtex 2, we(More)
This paper proposes a new technique to improve bit error performance of the min-sum decoding algorithm for low density parity check codes. The proposed technique is based on two way normalization of min-sum LDPC decoding algorithm. The variable message is modified by two normalization factors to achieve the optimum approximation for the magnitude(More)
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