Sven Hampel

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In this paper, the design of a fully synthesizable time-to-digital converter (TDC) for digital phase locked loops including the underlying design approach is proposed. In contrast to the traditional way of full-custom implementation, the presented design flow is based on generic RTL description and VLSI tools for synthesis and automated place and route.(More)
In this paper we present a method for analysis of phase noise in logic circuits. This method allows the design and verification of phase noise critical circuits using a digital toolchain, significantly reducing the design time and effort compared to the traditional approach using analog tools such as SPICE simulation. It is based on a set of(More)
This paper presents the design flow for a radio frequency multi-modulus divider, located in a digital phase-locked loop, using a standard-cell library in 28 nm CMOS technology. The flow is based on VLSI tools for synthesis and automated place and route. The resulting design has a technology-independent fully behavioral description that allows fast(More)
We present a methodology for phase noise minimization of interconnects in radio frequency circuits, integrated into a commercial digital tool chain. Accurate estimates of the produced phase noise are derived using a lookup table approach, eliminating the need for analog simulations. A dynamic programming algorithm is utilized to produce the optimal tree(More)
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