Sushma R. Huddar

Learn More
With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we(More)
Enormous agricultural yield is lost every year, due to rapid infestation by pests and insects. A lot of research is being carried out worldwide to identify scientific methodologies for early detection/identification of these bio-aggressors. In the recent past, several approaches based on automation and image processing have come to light to address this(More)
With the ever increasing demand for secure transactions in banking and also in mail delivery systems, encryption and decryption using cryptography plays a very important role. Nowadays, with 90% of secure transactions occurring on smart phones and other hand-held devices, a low on-chip area and a high speed algorithm to perform the same becomes the need for(More)
While designing Fast Fourier Transform (FFT) cores, due to the use of multiplexers, memory, or ROMs, there is a substantial increase in power consumption and area. In order to increase speed and throughput, folding and pipelining methods have been approached by various existing designs. But the prime disadvantage of those architectures is the use of(More)
Discrete Hartley Transform (DHT) is one of the transform used for converting data in time domain into frequency domain using only real values. DHT can be used for highly modular and parallel processing of data in VLSI applications. We have proposed a new algorithm for calculating DHT of length 2N, where N=3 and 4. We have implemented multiplier as an(More)
In general, most of the operations performed by any complex system need a multiplier. Hence, multiplier based on FFT is the desired aim. In this paper, we have presented a review of parallel polynomial multiplier based on FFT using Indian Vedic mathematics. Parallel polynomial multipliers were optimized for throughput and area resources, respectively. These(More)
A Digital Down Converter (DDC), which is basically used to convert an intermediate frequency (IF) signal to its baseband form, forms an integral part of wireless receivers. The major functional blocks of a DDC constitute a mixer, Numerically Controlled Oscillator (NCO) and an FIR filter chain. In this paper, an area efficient and high speed DDC has been(More)
Matrix multiplication is the kernel operation used in many transform, image processing and digital signal processing application. In this paper, we have studied for parallel-parallel input and single output (PPI-SO), parallel-parallel input and multiple output (PPI-MO) and parallel-parallel fixed input and multiple output (PFI-MO) matrix-matrix(More)
High performance digital adder with less power consumption and reduced area is a fundamental design issues for advanced processors. Carry Select Adder (CSA) is one of the fastest adder used in many processors to perform fast arithmetic function. Many different adder architecture designs have been developed to increase the efficiency of the adder. As we know(More)
  • 1