Sushant Suryagandh

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A new methodology is proposed to extract self-heating free I-V curves, including the substrate current, of SOI MOSFETs based on triple-temperature, regular DC measurement. It is verified to be accurate with Hspice simulations and suitable for SPICE model parameter extraction. It is also demonstrated that extraction of self-heating free I-V curves is not(More)
The impact of the gate induced drain leakage and impact ionization currents on hysteresis of PD FB SOI circuits is examined, and a physical understanding is provided. Measured silicon data from 90nm and 65nm PD SOI technologies indicate that both components dominate in the substrate currents at zero gate voltage and non-zero drain voltages. Substrate(More)
Stressors have been used since 90 nm technology to improve device performance to overcome the limitations of scaling. The stressors, including, - CPEN, TPEN, SMT, and e-SiGe to improve NMOS and PMOS drive current exhibit proximity dependence. In addition, unintentional stressors such as STI edge proximity introduce additional layout dependencies. Two(More)
Speculative SPICE models (also referred to as evaluation-level or guess models), which are extracted based on projected device electrical characteristics (called `targets¿) rather than actual measurement data, are required to support concurrent IC designs. The self-heating effect in silicon-on-insulator (SOI) technologies presents additional challenges in(More)
Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior,(More)
Analog design uses transistors with longer channel length for high performance. Transconductance (gm), Output Resistance (Rout) and Intrinsic Gain (gm x Rout) form the metric to gauge this performance. It is critical to design these circuits for manufacturing variability. This work presents a systematic compact modeling approach to capture analog variation(More)
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