Suriyaprakash Natarajan

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An efficient crosstalk target identification framework called XIDEN has been developed that is used prior to the computationally expensive processes of crosstalk validation and test generation. XIDEN is mainly composed of a set of extractors and filters that together identify the prime crosstalk targets. These prime targets include all error producing(More)
Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be identified. This paper proposes an iterative sampling method to identify these faults in large-scale analog(More)
W e address the testing of delay faults in domino circuits that contain complex gates. The diflerent ways in which these faults can cause errors are demonstrated. We identify structures in both the evaluate and the precharge logic that should be tested for delay faults. W e propose conditions to genemte delay tests for them, and outline extensions to handle(More)
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across latches results in signals which propagate across multiple clock cycles along paths with multiple latches. These paths need to be tested for delay failures to ensure reliability of(More)
Wafer-level spatial correlation modeling of probetest measurements has been explored in the past as an avenue to test cost and test time reduction. In this work, we first improve the accuracy of a popular Gaussian process-based wafer-level spatial correlation method through two key enhancements: (i) confidence estimation-based progressive sampling, and,(More)