Suresh Kumar Devanathan

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We propose a simulation-based sequential automatic test pattern generation (ATPG) method for single stuck-at faults using the wavelet transform and linear reverse order restoration (LROR) compaction. Sequential ATPG is such a difficult problem that nearly all industrial circuits are tested using full-scan design and combinational ATPG. We describe the(More)
—We propose a new partial-scan algorithm, the first to use toggling rates of the flip-flops (analyzed using DSP methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. This improves the testability of the circuit-under-test (CUT). Entropy is maximized throughout the circuit to maximize the information flow (the principle of(More)
We propose a sequential built-in self-test (BIST) hardware pattern generator using Haar wavelets, linear feedback shift registers (LFSRs), modulation, correlation and biasing hardware that produces higher fault efficiencies (FEs) than existing sequential BIST methods. We generate random bit sequences for primary inputs (PIs), which are modulated by Haar(More)
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