Sunjaya Djaja

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544 0740-7475/04/$20.00 © 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers AS SYSTEM-ON-A-CHIP TECHNOLOGY MATURES, including sensor arrays on the chip itself is increasingly valuable, allowing more system integration, higher operating speeds, and the ability to include many sensor types in a single substrate for(More)
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtained by splitting the photodiode and readout transistors into two parallel operating devices, while keeping a common row select transistor. This creates a redundant APS that is(More)
Digital imaging detectors are growing larger in silicon area and pixel count, which increases fabrication time defects, reducing yield, hence increasing costs and limiting area. In harsh environments, like high radiation conditions, what used to work might fail with time. Fault tolerant Active Pixel Sensors have been created by splitting the photodiode and(More)
Reliability and manufacturing costs due to defects is a significant problem with image sensors and the ability to recover from a fault would alleviate some of these costs. A fault-tolerant APS has been designed by splitting the APS pixel into two halves operating in parallel, where the photo sensing element has been divided in two and the readout(More)
As the pixel counts of digital imagers increase, the challenge of maintaining high yields and ensuring reliability over an imager’s lifetime increases. A fault tolerant active pixel sensor (APS) has been designed to meet this need by splitting an APS in half and operating both halves in parallel. The fault tolerant APS will perform normally in the no defect(More)
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