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Through-Silicon-Via (TSV) is the enabling technology for the fine-grained 3D integration of multiple dies into a single stack. These TSVs occupy non-negligible silicon area because of their sheer size. This significant silicon area occupied by the TSVs and the interconnections made to the TSVs greatly affect area, power, performance, and reliability of 3D(More)
This paper focuses on low-power and low-slew clock network design and analysis for through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate the impact of the TSV count and the TSV resistance–capacitance (RC) parasitics on clock power consumption. Several techniques are introduced to reduce the clock power consumption and(More)
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. The widely used TSV(More)
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite that TSV count is much smaller compared with the gate count. Two approaches are proposed to alleviate TSV-to-TSV coupling, namely TSV(More)
This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 μ -diameter, 6 μ -height through-silicon vias (TSVs) and μ -diameter face-to-face bond pads.(More)
Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to offer new levels of efficiency, power, performance, and form-factor advantages over the conventional 2D IC. However, 3D IC involves disruptive manufacturing technologies compared to conventional 2D IC. TSVs cause significant thermomechanical stress that may seriously(More)
Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with prebond testability because designers can avoid stacking defective dies with good ones. However, pre-bond testability presents unique challenges to 3D clock tree design. First, each die needs a complete 2D clock tree for the pre-bond(More)
532 0740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers TH E SOC P A R A D I G M is a system integration approach that integrates large numbers of transistors as well as various mixed-signal active and passive components onto a single chip. However, the systems community is beginning to realize that(More)
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides a theoretical background to efficiently construct a buffered 3D clock tree that minimizes and balances the skew values under two distinct non-uniform thermal profiles. Our clock(More)
Physical design automation for the new emerging mixed-signal System-on-Package (SOP) technology requires a new kind of floorplanner—it must place both active components such as digital IC, analog ICs, memory modules, MEMS, and optoelectronic modules, and embedded passive components such as capacitors, resistors, and inductors in a multi-layer packaging(More)