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Physical design automation for the new emerging mixed-signal System-on-Package (SOP) technology requires a new kind of floorplanner—it must place both active components such as digital IC, analog ICs, memory modules, MEMS, and opto-electronic modules, and embedded passive components such as capacitors, resistors, and inductors in a multi-layer packaging(More)
In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-performance quality offered by flat implementations (unlike block-level M3D), and zero total silicon area(More)
— Imbalanced distribution of workloads across a chip multiprocessor (CMP) constitutes wasteful use of resources. Most existing load distribution and balancing techniques employ very limited hardware support and rely predominantly on software for their operation. This paper introduces IsoNet, a hardware-based conflict-free dynamic load distribution and(More)
Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1-4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at(More)
Through-Silicon-Via (TSV) is the enabling technology for the fine-grained 3D integration of multiple dies into a single stack. These TSVs occupy non-negligible silicon area because of their sheer size. This significant silicon area occupied by the TSVs and the interconnections made to the TSVs greatly affect area, power, performance, and reliability of 3D(More)
—This paper presents the first multiobjective microar-chitectural floorplanning algorithm for high-performance processors implemented in two-dimensional (2-D) and three-dimensional (3-D) ICs. The floorplanner takes a microarchitectural netlist and determines the dimension as well as the placement of the functional modules into single-or multiple-device(More)
Individual dies in 3D integrated circuits are connected using through-silicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power overhead. However, the effects of TSV overheads have not been studied thoroughly in the literature. In this paper, we analyze the impact of TSVs on silicon area and wirelength. We(More)
In this paper, we propose a unified approach to partitioning, floorplanning, and retiming for effective and efficient performance optimization. The integration enables the partitioner to exploit more realistic <i>geometric delay model</i> provided by the underlying floorplan. Simultaneous consideration of partitioning and retiming under the geometric delay(More)
— 3D circuits have the potential to improve performance over traditional 2D circuits by reducing wirelength and interconnect delay. One major problem with 3D circuits is that their higher device density due to reduced footprint area leads to greater temperatures. Thermal vias are a potential solution to this problem. This paper presents a thermal via(More)