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As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. The widely used TSV(More)
Physical design automation for the new emerging mixed-signal System-on-Package (SOP) technology requires a new kind of floorplanner—it must place both active components such as digital IC, analog ICs, memory modules, MEMS, and opto-electronic modules, and embedded passive components such as capacitors, resistors, and inductors in a multi-layer packaging(More)
— Imbalanced distribution of workloads across a chip multiprocessor (CMP) constitutes wasteful use of resources. Most existing load distribution and balancing techniques employ very limited hardware support and rely predominantly on software for their operation. This paper introduces IsoNet, a hardware-based conflict-free dynamic load distribution and(More)
Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to offer new levels of efficiency, power, performance, and form-factor advantages over the conventional 2D IC. However, 3D IC involves disruptive manufacturing technologies compared to conventional 2D IC. TSVs cause significant thermomechanical stress that may seriously(More)
The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high density device integration at the individual transistor-level. In this paper we demonstrate the power benefits of transistor-level monolithic 3D designs. We first build a cell library that consists of 3D gates and model their timing/power characteristics. Next, we(More)
In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-performance quality offered by flat implementations (unlike block-level M3D), and zero total silicon area(More)
TSV-to-TSV coupling is a new parasitic element in 3D ICs and can become a significant source of signal integrity problem. Existing studies on its extraction, however, becomes highly inaccurate when handling more than two TSVs on full-chip scale. In this paper we investigate the multiple TSV-to-TSV coupling issue and propose an accurate model that can be(More)
Through-Silicon-Via (TSV) is the enabling technology for the fine-grained 3D integration of multiple dies into a single stack. These TSVs occupy non-negligible silicon area because of their sheer size. This significant silicon area occupied by the TSVs and the interconnections made to the TSVs greatly affect area, power, performance, and reliability of 3D(More)
Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1-4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at(More)