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In motion estimation, fast algorithms usually lead to an irregular searching flow, and the power reduction on architecture level is constrained for poor data reuse (DR). In this paper, a parallel IME hardware for H.264/AVC is proposed to well combine the techniques on algorithm and architecture levels. The "2-D SAD Tree" is adopted to support intra- and(More)
A new SoC architecture for multimedia content analysis is implemented with 16mm<sup>2</sup> area in 90nm CMOS technology. It focuses on the co-acceleration of computer vision and machine learning algorithms, and two stream processors with massively parallel processing elements are integrated to achieve tera-scale performance. In the dual processor(More)
SWLMs, and then shifted and reused in SRA. 87.5% A 2.8 to 67.2mW H.264 encoder is implemented on a memory power of IME is thus saved. 12.8mM2 die with 0.1I8 tm CMOS technology. The proposed Figure 2 shows the proposed fractional-pixel ME (FME) parallel architectures along with fast algorithms and data engine. Different from the sequential half-then-quarter(More)
—Because video services become popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus suitable for mobile applications. In this paper, we target at a power-efficient H.264/AVC encoder. The main power consumption in(More)
—In this paper, a 2D-to-3D video conversion system capable of realtime conversion of 1920×1080p 2D video to 3D video is presented. System fuses global and local depth generation modules to generate depth image, and use depth image based rendering(DIBR) algorithm to render 3D video. The system is implemented both on software and hardware. Software is based(More)
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critical issue. Data reuse (DR) is a technique that recycles the data read from memory and can be used to reduce memory access power. In this paper, a systematic method of DR exploration(More)
—With the rapid growth of media-processing technologies and the advancement of semiconductor process, more and more multimedia applications are integrated into consumer electronics. However, in such highly complex system, the design time for the circuit designers does not reduce much as the process advances. We propose a novel hybrid pipeline design(More)
Scalable Video Coding (SVC) is an advanced video compression technique that can support temporal, spatial, and quality scalability to terminals with different network conditions. SVC adopts layered coding techniques to improve coding efficiency for spatial and quality scalability. Upsam-pling and inter-layer prediction are two important mechanisms to remove(More)
The concept of algorithm and architecture co-design is presented in this paper for realizing a low-power H.264 encoder. At first, the three-level memory hierarchy of a video coding system was shown for power analysis. The main power sources of a chip are data processing power and memory access power. Power reduction techniques on the algorithm-level and(More)
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