Sung-Fang Tsai

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—In an H.264/AVC video encoder, integer motion estimation (IME) requires 74.29% computational complexity and 77.49% memory access and becomes the most critical component for low-power applications. According to our analysis, an optimal low-power IME engine should be a parallel hardware architecture supporting fast algorithms and efficient data reuse (DR).(More)
—A new machine learning SoC (MLSoC) for multi-media content analysis is implemented with 16-mm 2 area in 90-nm CMOS technology. Different from traditional VLSI architectures, it focuses on the coacceleration of computer vision and machine learning algorithms, and two stream processors with massively parallel processing elements are integrated to achieve(More)
—Because video services become popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus suitable for mobile applications. In this paper, we target at a power-efficient H.264/AVC encoder. The main power consumption in(More)
—In this paper, a 2D-to-3D video conversion system capable of realtime conversion of 1920×1080p 2D video to 3D video is presented. System fuses global and local depth generation modules to generate depth image, and use depth image based rendering(DIBR) algorithm to render 3D video. The system is implemented both on software and hardware. Software is based(More)
— In motion estimation, fast algorithms usually lead to an irregular searching flow, and the power reduction on architecture level is constrained for poor data reuse (DR). In this paper, a parallel IME hardware for H.264/AVC is proposed to well combine the techniques on algorithm and architecture levels. The " 2-D SAD Tree " is adopted to support intra-and(More)
Scalable Video Coding (SVC) is an advanced video compression technique that can support temporal, spatial, and quality scalability to terminals with different network conditions. SVC adopts layered coding techniques to improve coding efficiency for spatial and quality scalability. Upsam-pling and inter-layer prediction are two important mechanisms to remove(More)
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critical issue. Data reuse (DR) is a technique that recycles the data read from memory and can be used to reduce memory access power. In this paper, a systematic method of DR exploration(More)
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