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This work presents a method to reliably perform computations in the presence of hard faults arising from aggressive technology scaling, and design defects from human error. Our method is based on an observation that a single Turing-complete instruction can mirror the semantics of any other instruction. One such instruction is the subleq instruction, which(More)
In this paper, we propose a new, low hardware overhead solution for permanent fault detection at the microarchitecture/instruction level. The proposed technique is based on an ultra-reduced instruction set co-processor (URISC) that, in its simplest form, executes only <i>one</i> Turing complete instruction --- the subleq instruction. Thus, <i>any</i>(More)
Dynamic power management for multi-core system on chip (MPSoC) platforms has become an increasingly critical design problem. In this paper, we present EmPower, an FPGA based rapid prototyping framework for dynamic power management algorithms targeted at MPSoC platforms. EmPower supports two advanced power management techniques (per-core dynamic frequency(More)
Dynamic power management for multi-core system on chip (MPSoC) platforms has become an increasingly critical design problem. In this paper, we present EmPower, an FPGA based emulation, validation and prototyping framework for dynamic power management research targeted at MPSoC platforms. EmPower supports two advanced power management features -- per-core(More)