Sun Kyoung Kang

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We present a new 0.35um BCDMOS technology with a capability of 8 to 60V NLDMOS. The proposed process do not need level shifter, charge pump and boost up due to the same gate oxide thickness with logic 5V CMOS. And the Rsp of the proposed 24V NLDMOS structure is lower by 46% than conventional structure. The process has no thermal budget modification but use(More)
We present a new 0.3 5um BCD technology with a capability of 8 to 60V p-ch LDMOS. The proposed p-ch LDMOS employs the S-PWELL in the p-epi region to ensure high breakdown voltage and low on-resistance. The Rsp of the proposed 60V p-ch LDMOS is lower by 42% than conventional one. And we modified the 300Å gate oxide of the original p-ch LDMOS to(More)
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