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– System-on-Chip (SoC) architectures integrate several heterogeneous components onto a single chip. These components provide various capabilities such as dynamic voltage scaling, reconfiguration, multiple power states, etc. that can be exploited for performance optimization during application design. We propose a Generic Model (GenM) which captures the(More)
Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application design using heterogeneous embedded systems. However, more choices during application design results in a large design space that must be traversed efficiently. In this paper, we(More)
In addition to integrating different Intellectual Property cores, heterogeneous embedded systems provide several architecture knobs such as voltage, operating frequency, configuration, etc. that can be varied to optimize performance. Such flexibilities results in a large design space making system optimization a very challenging task. Moreover, such systems(More)
– Reconfigurable architectures such as FPGAs are flexible alternatives to DSPs or ASICs used in mobile devices for which energy is a key performance metric. Re-configurable architectures offer several parameters such as operating frequency, precision, amount of memory, number of computation units, etc. These parameters define a large design space that must(More)
We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration , and low level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by(More)
For an FPGA designer, several choices are available in terms of target FPGA devices, IP-cores, algorithms, synthesis options, runtime reconfiguration, degrees of parallelism, among others, while implementing a design. Evaluation of design alternatives in the early stages of the design cycle is important because the choices made can have a critical impact on(More)
Model Integrated Computing (MIC) promotes the use of models as a " backbone " of model-integrated system development. In this paper, we study the use of MIC to design a heterogeneous high-performance, low-power embedded system. Use of MIC enabled us to accommodate evolving performance requirements, target hardware specification, and mission scenarios while(More)
Duty cycle is the proportion of time a device is active. Therefore, based on the duty cycle specification, application (implemented using the device) execution can be modeled as alternate active and inactive phases. For FPGAs, during inactive phases, energy is dissipated due to leakage current and clock signal distribution. If the duration of the inactive(More)