Learn More
This paper presents a modular and extensible high-level synthesis research system, called SPARK, that takes a be-havioral description in ANSI-C as input and produces syn-thesizable register-transfer level VHDL. SPARK uses par-allelizing compiler technology developed previously to enhance instruction-level parallelism and re-instruments it for high-level(More)
— Previous homography-based visual servo controllers have been developed using an error system that contains a singularity resulting from the representation of the rotation matrix. For some aerospace applications such as visual servo control of satellites or air vehicles, the singularity introduced by the rotation representation may be restrictive. To(More)
— Internet enabled wireless devices continue to proliferate and are expected to surpass traditional Internet clients in the near future. This has opened up exciting new opportunities in the mobile e-commerce market. However, data security and privacy remain major concerns in the current generation of " wireless web " offerings. All such offerings today use(More)
We present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a pre-synthesis phase and during scheduling, with the objective of optimizing the results of synthesis and reducing the impact of control flow constructs on the quality of(More)
Since its proposal by Victor Miller [17] and Neal Koblitz [15] in the mid 1980s, Elliptic Curve Cryptography (ECC) has evolved into a mature public-key cryptosystem. Offering the smallest key size and the highest strength per bit, its computational efficiency can benefit both client devices and server machines. We have designed a programmable hardware(More)
Several coarse-grain reconfigurable architectures proposed recently consist of a large number of processing elements (PEs) connected in a mesh-like network topology. We study the effects of three aspects of network topology exploration on the performance of applications on these architectures: (a) changing the interconnection between PEs, (b) changing the(More)
—The quality of synthesis results for most high-level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. This leads to a need for high-level and compiler transformations that overcome the effects of programming style on the quality of generated circuits. To address this issue, we(More)
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. Wepresent a technique called loop shifting that incrementally exploits loop level parallelism across iterations by shifting and compacting operations across loop iterations. Our experimental(More)
In this paper, we propose a new framework to perform motion compression for time-dependent 3D geometric data. Temporal coherence in dynamic geometric models can be used to achieve significant compression, thereby leading to efficient storage and transmission of large volumes of 3D data. The displacement of the vertices in the geometric models is computed(More)
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a pro-grammable co-processor to reduce the computational load on the main processor core. We present an interface synthesis approach that enables us to do hardware-software codesign for such FPGA-based platforms. The approach is based on a novel memory(More)