Sumant Kale

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Stringent test-time and yield targets together with increased embedded memory content has resulted in increased power and area of memory self-test and repair logic. It is common for high performance IP cores (CPU/DSP/GPU/etc.) to have embedded BIST datapath (DP) that is shared with functional logic to minimize the IP BIST area overhead and ease IP(More)
Innovative solutions have been proposed to reduce the test cost of SOC designs. STUMPS (self-test using PRPG and MISR structures) architecture based logic BIST (built-in self-test) is one such popular solution which attempts to reduce the cost of scan based tests by exploiting shorter scan chains in the design. To address the lower test coverage attainable(More)
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