Suk-Kyu Ryu

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In this work, we propose an efficient and accurate full-chip thermo-mechanical stress and reliability analysis framework. To the best of our knowledge this is the first such system which enables full-chip stress simulation as compared to existing commercial Finite Element Analysis (FEA) tools which can only simulate very small cross-sections at a time. Our(More)
Three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective approach to overcome the wiring limit beyond the 32 nm technology node. Due to the mismatch of thermal expansion between the via material and Si, thermal stresses ubiquitously exist in the integrated 3-D structures. The thermal stresses can be significant to(More)
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