Learn More
In this work, we propose an efficient and accurate full-chip thermo-mechanical stress and reliability analysis framework. To the best of our knowledge this is the first such system which enables full-chip stress simulation as compared to existing commercial Finite Element Analysis (FEA) tools which can only simulate very small cross-sections at a time. Our(More)
—Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key(More)
Mobility and Dit distributions for p-channel MOSFETs with HfO2/LaGeOx passivating layers on germanium " Stubborn " triaminotrinitrobenzene: Unusually high chemical stability of a molecular solid to 150 GPa Stress migration risk on electromigration reliability in advanced narrow line copper interconnects Stress migration model for Cu interconnect reliability(More)
—Three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility and raise serious reliability concerns. In this paper, the(More)
Mechanism for resistive switching in an oxide-based electrochemical metallization memory Appl. The role of eddy currents and nanoparticle size on AC magnetic field–induced reflow in solder/magnetic nanocomposites J. Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique Appl.(More)
—This paper investigates two key aspects of thermomechanical reliability of through-silicon vias (TSV) in 3D interconnects. One is the piezoresistivity effect induced by the near surface stresses on the charge mobility for p-and n-channel MOSFET devices. The other problem concerns the interfacial delamination induced by thermal stresses including the pop-up(More)
Three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective approach to overcome the wiring limit beyond the 32 nm technology node. Due to the mismatch of thermal expansion between the via material and Si, thermal stresses ubiquitously exist in the integrated 3-D structures. The thermal stresses can be significant to(More)
Development of the heat treatment system for the 40 T hybrid magnet superconducting outsert Rev. Abstract. Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three-dimensional (3-D) integration with through-silicon-vias (TSVs) has(More)
Strain-compensation measurement and simulation of InGaAs/GaAsP multiple quantum wells by metal organic vapor phase epitaxy using wafer-curvature Temperature stability of the pentacene thin-film phase Appl. Ab-initio aprroach to the electronic, structural, elastic, and finite-temperature thermodynamic properties of Ti2AX (A=Al or Ga and X=C or N) Micro-scale(More)
—An analytical approach to predict initiation and growth of interfacial delamination in the through-silicon via structure is developed by combining a cohesive zone model with a shear-lag model. Two critical temperatures are predicted for damage initiation and fracture initiation, respectively. It is found that via extrusion significantly increases beyond(More)