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Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design, in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a(More)
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ideas, many challenges remain in applying SBST to realistic embedded processors. We propose a systematic(More)
In order to support diverse application requirements, a new standard called IEEE 802.11e is being proposed to improve quality of service in wireless LAN networks. There are, however, a few remaining challenges that need to be addressed in order to enable comprehensive QoS support using 802.11e. In this article we provide an overview of a few of these(More)
As an increasing number of electronic systems are powered by batteries, battery life becomes a primary design consideration. Maxiimizing battery life requires system designers to develop an understanding of the capabilities and limitations of the batteries that power such systems, and to incorporate battery considerations into the system design process.(More)
System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies [3,4], as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects(More)
—At-speed testing of gigahertz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost high-quality self-test methodologies that can be used by processors to test themselves at-speed. Currently, built-in self-test (BIST) is the primary self-test methodology available. While memory(More)
—This paper presents a novel system-level performance analysis technique to support the design of custom communication architectures for system-on-chip integrated circuits. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework(More)