Suhaimi Bahisham Jusoh

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
At-speed scan testing for intra-clock and inter-clock transition delay faults in a SOC design with multiple clock domains is an important and challenging issue. Current practice in industry usually applies a test scheme targeted on intra-clock transition fault delay testing (i.e., intra testing). In this paper a test scheme targeting both intra-clock and(More)
  • 1