Suching Hsu

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A novel self-biased PLL design incorporating a low-gain interpolated inverter-based ring oscillator VCO accomplishes several improvements for general purpose clock generation, namely lower bandwidth and lower short and medium-term accumulation jitter due to thermal noise and reference clock noise, while not sacrificing PSRR, area, and PVT insensitivity.(More)
This paper describes the design of a 1.2-mW, 0.027-mm<sup>2</sup> thermal sensor and its accompanying supply voltage regulator, both implemented in a Hi-K, metal gate, 32nm technology. The designs incorporated built-in run-time variability reduction schemes for improved manufacturability, which allowed the sensor to achieve an INL of &#x00B1;0.27&#x00B0;C(More)
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