Subhomoy Chattopadhyay

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Multi-chip modules are now required to achieve higher system speed and greater density than the traditional single chip packages mounted on printed circuit boards. Algorithms for placement of bare dies and and routing of their interconnections on MCM substrates are r eviewed in this paper. Comparisons are given to point out the strengths and weaknesses of(More)
Power has become one of the most important paradigms of design convergence for future microprocessor and ASIC/SOC designs in the 65nm and smaller geometries. The amount of logic that goes on a SOC is determined by the power envelope of the part for the applications that the part would support. In this tutorial I am presenting the importance of low power(More)
As AND-XOR network results in much better realization and requires fewer product terms than AND-OR realization, it network has encouraged researchers to look for efficient minimization and synthesis tools for their realization. Among several canonical representations of AND-XOR networks, popular and most testable one is the fixed polarity Reed Muller (FPRM)(More)
Power has become one of the most important paradigms of design convergence for future microprocessor and ASIC/SOC designs. In this tutorial we present the importance of low power microprocessor/SOC design from the high level microarchitectural, RTL, gate level to transistor level design. We cover the conflicting goals of performance vs low power, routinely(More)
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