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The <italic>false path</italic> problem is often referred to as the problem of detecting the longest <italic>sensitizable path</italic> (A path which is not a <italic>false path</italic> is a <italic>sensitizable path</italic>). The term &#8220;<italic>false path</italic>&#8221; is not clearly defined. In this paper, we first give a clear and precise(More)
Path extracting algorithms are a very important part of timing analysis approach. In this paper we designed and developed several algorithms which can generate the <italic>K</italic> most critical paths in a non-increasing order of their delays. The effectiveness of these algorithms is shown by some experimental results.
Much work has been done on the modeling of hardware resources; far fewer studies have been conducted on the impact of software systems on the underlying hardware. The authors address one such case in which blocking is present because of critical sections of code; this cannot be treated within the framework of product-form queuing network models. They show(More)
A file system tailored to the general needs of the office environment is proposed. This system supports large numbers of a wide variety of documents and inexact &#x2018;fuzzy&#x2019; queries on the documents. The file system is based on a multilevel file structure; the structure combines and extends multikey extendible hashing and signature files to create(More)
A new, fully-distributed protocol for integrated voice/data traffic in a local-area, random-access broadcast network is described. The protocol introduces a movable voice-data boundary to framed TDMA/CSMA and eliminates the requirement of system-wide synchronized clocks. The movable boundary is a major advantage in any system where fluctuations in voice and(More)
CAD databases have been used to store design data and to integrate design tools in IC/VLSI design systems. However, the requirements for a &#x201C;good&#x201D; CAD database are much more complex than those for a conventional database. Due to both the complexity of various design processes and the enormous amount of data involved in a practical CAD database,(More)
Due to the rapid progress in semiconductor technology, the number of gates that can be placed in a chip increases dramatically. Existing algorithms for timing analysis have difficulties when dealing with large designs. A new algorithm for timing analysis is proposed in this paper. This algorithm enumerates all the paths with delay greater than a given(More)