Subash Shankar

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Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal veriication, design, simulation, and testing. Program slicing is a static program analysis technique that allows an analyst to automatically extract(More)
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This paper describes a framework that allows for reasoning about and verification of concurrent statecharts with real-time constraints subject to semantic variations. The major problems addressed by this paper include the capture of multiple semantic variations of real-time statecharts, and the use of the resulting semantics for further analysis. Our(More)