Stevo Bailey

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8/12 – Present • Collaborating with a team of graduate students to design energy-efficient processors with fine-grained DVFS • Led the physical design of several RISC-V processors with integrated voltage regulators in 28nm FD-SOI • Leveraging fast scaling by developing novel DVFS algorithms that will improve energy efficiency Asynchronous Interfaces, ASIC(More)
— Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc–dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion efficiency. We propose a dynamic voltage and frequency scaling scheme with SC converters that achieves(More)
The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to complete large, complex designs on schedule using traditional rigid development flows. This article(More)
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