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Several strategies that were employed for developing next-generation embedded Hard IP are reviewed. Mixed signal Hard IP developed for a multi-protocol serial interface physical layer at 0.622Gbps to 3.125Gbps was redeployed for 0.622Gbps to 6.375Gbps data rates. Ensuring quality meant adopting a strongly modular approach to design and verification. The(More)
The system-level protocol verification of a high-end FPGA with an embedded high-speed serial interface (HSSI) poses challenges that are comparable to and arguably exceed those encountered in ASIC-like verification flows. A single high-end FPGA device with embedded transceivers is designed to provide dedicated hard intellectual property (IP) support for a(More)
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