Steven J. Koester

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integration technology S. J. Koester A. M. Young R. R. Yu S. Purushothaman K.-N. Chen D. C. La Tulipe, Jr. N. Rana L. Shi M. R. Wordeman E. J. Sprogis An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations(More)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing < 60 mV/decade.(More)
After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate(More)
Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of(More)
As the end draws near for Moore's law, the search for low-power alternatives to complementary metal-oxide-semiconductor (CMOS) technology is intensifying. Among the various post-CMOS candidates, spintronic devices have gained special attention for their potential to overcome the power and performance limitations of CMOS. In particular, all spin logic (ASL)(More)
We present a detailed study on the operation of a tunneling field-effect transistor (TFET) based on one-dimensional broken-gap heterostructure geometry. Using numerical simulations we show that less than 60mV/dec subthreshold swing can be obtained in this device along with MOSFET-like drive-currents. We further demonstrate that the 1D geometry is uniquely(More)
Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D(More)
We report record contact resistance and transconductance in locally back-gated black phosphorus p-MOSFETs with 7-nm thick HfO<sub>2</sub> gate dielectrics. Devices with effective gate lengths, L<sub>eff</sub>, from 0.55 to 0.17 &#x03BC;m were characterized and shown to have contact resistance values as low as 1.14 &#x00B1; 0.05 Q-mm. In addition, devices(More)
Graphene's unique optoelectronic properties have been exploited for many photonic applications. Here, we demonstrate a single graphene-based device that simultaneously provides efficient optical modulation and photodetection. The graphene device is integrated on a silicon waveguide and is tunable with a graphene gate to achieve a near-infrared(More)
Tunneling field-effect transistors (TFETs) are attracting a lot of interest because of their potential to reduce power dissipation in logic applications [1&#x2013;3]. Performance of TFETs is expected to improve with increasing electrostatic control as provided by ultra-thin body (UTB) based single-gate (SG), double-gate (DG), and nanowire based(More)