Foundation of rf CMOS and SiGe BiCMOS technologies This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal… (More)
− Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe)… (More)
Electrostatic Discharge (ESD) and Electrical Overstress (EOS) continue to impact semiconductor components and systems as technologies scale from micro-to nano-electronics. This paper focuses on the state of the art of electrostatic discharge (ESD) and electrical overstress (EOS), with an emphasis on failure mechanisms and testing. The tutorial provides a… (More)
Electrostatic discharge (ESD) protection and latchup issues in three dimensional (3-D) semiconductor chip systems is discussed for the first time. ESD protection in 3-D multi-chip systems will be important for both memory and system-on-chip (SOC) applications. Two types of 3-D semiconductor chips will be discussed; a first version introduces edge wiring,… (More)
A new metric, “Within ESD Bus Resistance” - a limitation on the ESD results due to power bus scaling, will be demonstrated with voltage drop simulation, failure analysis, SEM cross sections, HBM and MM ESD test results, and a novel ESD “resistance shunt” solution is demonstrated.