Steven H. Voldman

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This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process(More)
This paper is an overview of the methods used at the Burlington facility of the IBiVI iVIicroelectronlcs Division to improve channellength tolerance control in the manufacture of CMOS logic chips. We cover aspects of 1) the impact of channel-length control on chip performance, yield, and reliability; 2) our use of an electrical linewidth monitor which(More)
−Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe)(More)
Latchup! In this chapter, a brief overview of latchup is provided. We will provide a first quick look on what latchup is. As a starting point, this discussion will be followed by a summary of evolution, history, key innovations and patents. This chapter discusses the key innovations, contributions and patents associated with the process of understanding how(More)
  • S. H. Voldman
  • 2012 IEEE 11th International Conference on Solid…
  • 2012
In this Invited Paper, an overview of electrostatic discharge (ESD) and latchup challenges in analog and power applications will be discussed. Analog and power technologies continue to be a challenge for electrostatic discharge (ESD) protection and latchup. Different aspects of ESD and latchup development from technology, application spaces, device design,(More)
Electrostatic Discharge (ESD) and Electrical Overstress (EOS) continue to impact semiconductor components and systems as technologies scale from micro-to nano-electronics. This paper focuses on the state of the art of electrostatic discharge (ESD) and electrical overstress (EOS), with an emphasis on failure mechanisms and testing. The tutorial provides a(More)