Steven G. Rothweiler

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We propose a novel sequential delay optimization technique based on network flow methods that simultaneously exploits delays on all paths in the circuit. We view the sequential circuit as an interconnection of path segments with pre-specified delays. Path segments are bounded by flip-flops, primary inputs or primary outputs. Recognizing that a delay(More)
Bridge is a behavioral synthesis system being developed at AT&T Bell Laboratories. Two slicing techniques are implemented in this system to drive structural allocation; one is local slicing and the other is global slicing. Global slicing supports the synthesis of concurrent processes with a centralized control. A variable in a behavioral description can(More)
Retiming is an effective technique to optimize the performance of synchronous sequential circuits. This paper proposes a method to improve the effectiveness of retiming by transforming the sequential circuit. Bottlenecks which prevent retiming to achieve a desired clock period are identified. Conditions to eliminate the retiming bottlenecks are derived.(More)
The BECOME system for behavior level circuit synthesis is presented. BECOME accepts circuit models written in C-like behavior level modeling languages and synthesizes them into different technologies such as PLA, PLD and standard cells. The system assumes a finite state machine circuit model with an external view of only primary inputs and outputs. A(More)
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