Steve H.-C. Yen

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This paper addresses post-routing capacitance extraction duringperformance-driven layout.We first show how basic driversin process technology (planarization and minimum metal densityrequirements) actually simplify the extraction problem; wedo this by proposing and validating five "foundations" throughdetailed experiments with representative 0.18¿m process(More)
The T2K experiment observes indications of ν(μ) → ν(e) appearance in data accumulated with 1.43×10(20) protons on target. Six events pass all selection criteria at the far detector. In a three-flavor neutrino oscillation scenario with |Δm(23)(2)| = 2.4×10(-3)  eV(2), sin(2)2θ(23) = 1 and sin(2)2θ(13) = 0, the expected number of such events is 1.5±0.3(syst).(More)
We have developed a gate matrix layout synthesis tool which utilizes folding technique on both rows and columns. The conventional interval graph model and the recently proposed dynamic net-list representation can not fully depict circuit schematics such as inter-net connections. The incomplete representations may mislead the search process for an optimal(More)
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