Steve H.-C. Yen

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This paper addresses post-routing capacitance extraction duringperformance-driven layout.We first show how basic driversin process technology (planarization and minimum metal densityrequirements) actually simplify the extraction problem; wedo this by proposing and validating five "foundations" throughdetailed experiments with representative 0.18¿m process(More)
This paper addresses post-routing capacitance extraction during performance-driven layout. We rst show how basic drivers in process technology (planarization and minimum metal density requirements) actually simplify the extraction problem; we do this by proposing and validating ve \foundations" through detailed experiments with representative 0:18 m process(More)
We have developed a gate matrix layout synthesis tool which utilizes folding technique on both rows and columns. The conventional interval graph model and the recently proposed dynamic net-list representation can not fully depict circuit schematics such as inter-net connections. The incomplete representations may mislead the search process for an optimal(More)
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